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Please use this identifier to cite or link to this item: http://hdl.handle.net/2328/25768

Title: Design techniques for high performance asynchronous arithmetic operators
Authors: Fan, Xingcha
Burford, Richard G
Bergmann, Neil W
Keywords: Control systems
Logic design
Pipeline processing
Multiplying circuits
Issue Date: 1994
Publisher: Institute of Electrical and Electronics Engineers Computer Society (IEEE Publishing)
Citation: Fan, X., Burford, R.G. and Bergmann, N.W. 1994. Design techniques for high performance asynchronous arithmetic operators. 1994 Asia-Pacific Conference on Circuits and Systems (APCCAS), 127 - 132.
Abstract: High performance asynchronous arithmetic operator design techniques are proposed, which adopt some of the techniques commonly used in synchronous systems such as fast precharged logic and efficient latch design, while maintaining the features of localized and elastic pipelining control inherent in asynchronous design. A pipelined sixteen bit multiplier designed using these techniques is presented and its performance compared with several previously reported asynchronous and synchronous designs.
URI: http://hdl.handle.net/2328/25768
ISSN: 0780324404
Appears in Collections:Computer Science, Engineering and Mathematics - Collected Works

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