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Please use this identifier to cite or link to this item: http://hdl.handle.net/2328/25821

Title: An 180 MHz 16 bit multiplier using asynchronous logic design techniques
Authors: Burford, Richard G
Fan, Xingcha
Bergmann, Neil W
Keywords: Logic design
Multiplying circuits
Pipeline arithmetic
Issue Date: 1994
Publisher: Institute of Electrical and Electronics Engineers Computer Society (IEEE Publishing)
Citation: Burford, R.G., Fan, X. and Bergmann, N.W. 1994. An 180 MHz 16 bit multiplier using asynchronous logic design techniques. 1994 Proceedings of the IEEE Custom Integrated Circuits Conference, 215-218.
Abstract: A CMOS digital logic design technique is described which exploits the advantages of fast precharged logic and efficient latch design commonly used in synchronous systems while maintaining the features of localized control inherent in asynchronous design. A pipelined sixteen bit multiplier is presented and its performance compared with several previously reported asynchronous and synchronous designs.
URI: http://hdl.handle.net/2328/25821
ISBN: 0780318862
Appears in Collections:Computer Science, Engineering and Mathematics - Collected Works

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